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題 名 | Break Fault Testing in Programmable Logic Arrays=可程式邏輯陣列之中斷故障測試 |
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作 者 | 黃國豪; | 書刊名 | 電信研究 |
卷 期 | 27:1 1997.02[民86.02] |
頁 次 | 頁131-155 |
分類號 | 448.532 |
關鍵詞 | 中斷故障模型; 可程式邏輯陣列; 自動測試樣本產生器; Break fault model; Programmable logic array; PLA; Automatic test pattern generation; ATPG; |
語 文 | 英文(English) |
中文摘要 | 傳統的可程式邏輯陣列之故障模型是交錯點故障(Crosspoint Fault),線固結 故障( Stuck-at Fault )及橋故障( Bridge Fault )。目前已經有很多的可程式邏輯陣 列之測試技術了,但是這些技術主要都是針對這些傳統的故障模型所設計的。不幸的是這些 技術並不能完全應用在中斷故障發生時,更不幸的是中斷故障的發生率又很高。因此考慮中 斷故障對提高可程式邏輯陣列之測試品質而言是非常重要的!在本論文中將分析中斷故障的 特性,並提出一套自動產生完整測試樣本的方法,此方法經實驗証實確實可提供快速又有效 率之測試樣本並達成最高之故障偵測率! |
英文摘要 | The conventional fault models of PLA's are crosspoint, stuck-at and bridging fault models Many techniques for PLA testing based on these fault models were proposed in the past. However, these techniques can not be applied to the break fault model due to the memory behavior. Unfortunately, it was shown that break faults are of frequent occurrence. Thus, considering break fault model is important to enhance the quality of PLA testing. In this paper, the behavior of break faults in PLAs is analyzed in detail and a complete PLA break fault ATPG system, PLABEK, is proposed. Experimental results show that PLABEK can generate very compact complete test sequences for break faults of PLAs very fast. |
本系統中英文摘要資訊取自各篇刊載內容。