頁籤選單縮合
題名 | A Via Reducer of Routed Channel= |
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作者 | 黃宗柱; |
期刊 | 中州學報 |
出版日期 | 19951000 |
卷期 | 8 1995.10[民84.10] |
頁次 | 頁168-174 |
分類號 | 448.57 |
語文 | eng |
關鍵詞 | CAD; Channel router; PCB; VLSI; Via; Benchmark; Graph; |
英文摘要 | It is usually our aim to reduce the VIA number not only in PCB but also in VLSI. This algorithm adopts a weighted graphic and several heuristics to reduce the VIA number of a routed channel. |
本系統之摘要資訊系依該期刊論文摘要之資訊為主。