頁籤選單縮合
題 名 | A Via Reducer of Routed Channel |
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作 者 | 黃宗柱; | 書刊名 | 中州學報 |
卷 期 | 8 1995.10[民84.10] |
頁 次 | 頁168-174 |
分類號 | 448.57 |
關鍵詞 | CAD; Channel router; PCB; VLSI; Via; Benchmark; Graph; |
語 文 | 英文(English) |
英文摘要 | It is usually our aim to reduce the VIA number not only in PCB but also in VLSI. This algorithm adopts a weighted graphic and several heuristics to reduce the VIA number of a routed channel. |
本系統中英文摘要資訊取自各篇刊載內容。