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題 名 | Design of Reliable CMOS Phase Locked Loops |
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作 者 | Wey, Chin-Long; Huang, Chi-Shu; | 書刊名 | International Journal of Electrical Engineering |
卷 期 | 14:3 2007.06[民96.06] |
頁 次 | 頁195-206 |
分類號 | 448.5 |
關鍵詞 | Gate-oxide defects; Phase-locked loops; Stress test; Extreme-voltage stress test; Reliability enhancement; |
語 文 | 英文(English) |
英文摘要 | Yield and reliability are two factors affecting the profitability of semiconductor manufacturing. There are a number of physical failure mechanisms that can affect the reliability of CMOS integrated circuits (ICs). Gate-oxide defects are the major causes of the reliability problems for CMOS ICs. The industry standard methods for screening infant mortality have high-temperature burn-in and extreme-voltage screening. However, the added manufacturing cost for burn-in screening may range from 5% to 40% of the total product cost. Two test approaches have been commonly used for extreme-voltage screening: (i) the 01-test; and (ii) the Iddq-test. In particular, the Iddq-tests are currently used with the burn-in screening to meet the required reliability of semiconductor products. This study demonstrates that a conventional PLL may pass the popular Iddq-tests in the presence of gate-oxide defects, causing the PLL to have a low reliability. This paper presents a first-ever reliable CMOS PLL for gate-oxide reliability enhancement. With inserting switches to the original PLL, the modified PLL can be fully stressable and thus enhance reliability. |
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