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題名 | High-Level Synthesis for Minimum-Area Low-Power Clock Gating= |
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作者 | 黃世旭; 凃雯斌; 李秉泓; Huang, Shih-hsu; Tu, Wen-pin; Li, Bing-hung; |
期刊 | Journal of Information Science and Engineering |
出版日期 | 20120900 |
卷期 | 28:5 2012.09[民101.09] |
頁次 | 頁971-988 |
分類號 | 448.57 |
語文 | eng |
關鍵詞 | Electronic design automation; High-level synthesis; Clock gating; Sequential circuits; Area minimization; |