頁籤選單縮合
題名 | Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization= |
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作者 | 黃世旭; 程駿華; 曾大誠; Huang, Shih-hsu; Cheng, Chun-hua; Tzeng, Da-chen; |
期刊 | Journal of Information Science and Engineering |
出版日期 | 20091100 |
卷期 | 25:6 2009.11[民98.11] |
頁次 | 頁1707-1722 |
分類號 | 448.532 |
語文 | eng |
關鍵詞 | Electronic design automation; Clock skew scheduling; High-level synthesis; Power gating; Mixed integer linear programming; |