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題名 | 應用於三維堆疊記憶體堆疊層選擇之控制電路設計=The Control Circuit Design for the Tier Selection of Three-dimensional Stacked Memory |
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作者 | 吳明學; 羅崑崙; 陳振岸; 陳宜文; Wu, Ming-hsueh; Luo, Kuo-len; Chen, Chen-an; Chen, Yee-wen; |
期刊 | 電腦與通訊 |
出版日期 | 20111000 |
卷期 | 141 2011.10[民100.10] |
頁次 | 頁67-74 |
分類號 | 448.57 |
語文 | chi |
關鍵詞 | 三維堆疊記憶體; 線性回饋位移暫存器; 識別碼; 識別碼產生器; 3-D stacked memory; Linear feedback shift register; LFSR; Identity code; ID; ID code generator; |
中文摘要 | 三維晶片具有較短連線長度與較高系統運作速率的優點,對於記憶體而言,更可藉穿矽孔(TSV)技術,簡單地將數顆完全一樣的記憶體晶片堆疊起來。本控制電路設計之目的為提供一個以三維堆疊之數層記憶體晶片,可有效地選擇任一層堆疊晶片的技術,以進行資料存取。其電路設計應用線性回饋位移暫存器電路可產生循環序列的概念,可產生不重複且可預測的識別碼數列,以之為啟動晶片用途。相較於其它堆疊記憶體堆疊晶片選擇方法,可節省晶片在TSV製作與識別碼產生器的面積,而僅付出少許延遲時間之代價。 |
英文摘要 | The shorter interconnection length and higher operation speed are the main advantages of three-dimensional integration circuits (3-D ICs). By using the technology of through-silicon-via (TSV), the memory dies can be easily stacked for 3-D IC design application. Based on the concept of linear feedback shift register (LFSR), this paper proposes a control circuit to effectively select any tier of the 3-D stacked memory for data accessing. The identity code (ID) generator, which can generate unrepeatable and predictable series codes to enable the stacked memories for tier selection, is the key component of the proposed method. Compared with the previous works, the proposed method has good performance in area overhead with less delay time penalty. |
本系統之摘要資訊系依該期刊論文摘要之資訊為主。