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題 名 | 高效能低壓降線性穩壓器之分析與實作=Analysis and Implementation of High Performance Low Dropout Liner Regulator |
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作 者 | 李民慶; 王清松; 陳漢儒; 陳新泓; 李霈穎; | 書刊名 | 亞東學報 |
卷 期 | 29 2009.06[民98.06] |
頁 次 | 頁81-89 |
分類號 | 448.532 |
關鍵詞 | 低壓降線性穩壓器; 線調節率; 負載調節率; 誤差放大器; 溫度係數; Low dropout linear regulator; Line regulation; Load regulation; Error amplifier; Temperature coefficient; |
語 文 | 中文(Chinese) |
中文摘要 | 摘要 低壓降線性穩壓器(LDO),擁有低雜訊、體積 小之特性,更因其效能之提升,近年來成為低功率 穩壓與電源管理積體電路之主流,本文針對組成一 高效能LDO 之架構:精準參考電電源電路、功率 電晶體、誤差放大器以及回授電阻之設計加以分 析、最後利用TSMC 0.35um CMOS 製程技術模 擬、設計完成一晶片面積約0.936 0.804mm2 、 消耗功率低於0.21mW ,且輸入電壓可從1.7V 至 3.3V ,線電壓調節率約0.43mV /V ,輸出電流可 從0mA至100mA,負載調節率約5mV / mA 以下, 輸出電壓可穩定在1.5V 之高效能LDO。此外整體 LDO 閉迴路之頻率響應、穩定度與溫度係數等問 題,也在本文中加以分析。 |
英文摘要 | Abstract Low Dropout Linear Regulator (LDO) is main structure of low power management integrated circuit in recent years, due to it’s low noise, high power density and improving power efficiency characteristics. In this paper, the main components within high performance LDO consist of a precision bias reference, power PMOS transistor, an error amplifier and feedback circuit are analyzed and design in detail. The proposed high performance LDO with a chip area of 0.9360.804mm2 , power dissipation of 0.21mW is designed and fabricated in a 2P4M TSMC 0.35-um CMOS process. Experimental result show that the high performance LDO functions properly with input voltage from 1.7V to 3.3V , provides an output voltage of 1.5V , with 0.43mV /V line regulation and 5mV /mA load regulation (output current from 0 ~ 100mA variation). The overall open-loop frequency response, stability of OPA and temperature coefficient are analyzed and discussed in this paper. |
本系統中英文摘要資訊取自各篇刊載內容。