頁籤選單縮合
題 名 | A High-Performance Programmable Scheduling Engine for ATM Switches |
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作 者 | Chi, Hsin-Chou; Wu, Chia-Ming; Fu, Kuo-Yao; | 書刊名 | 網際網路技術學刊 |
卷 期 | 8:4 2007.10[民96.10] |
頁 次 | 頁487-492 |
分類號 | 448.5 |
關鍵詞 | Scheduler; ATM switch; VLSI; QoS; |
語 文 | 英文(English) |
英文摘要 | ATM networks provide high-throughput low-latency communication for various types of applications, such as voice, video, and multimedia. ATM switches with quality of service are the key components in these networks. In this paper, the VLSI design and implementation of a scheduling engine for ATM switches are presented. This scheduling engine can efficiently arbitrate cells from input to output ports in the ATM switch. The scheduling engine efficiently compares the information of cells and determines which cell can be sent to the output port. An important feature of the engine is programmability. Using some programmable options implemented in the hardware, the scheduling engine is flexible enough to perform different scheduling schemes. With the proposed architecture, ATM switches can satisfy several scheduling requirements and achieve high throughput. Our design has been implemented in a VLSI chip to validate the idea. |
本系統中英文摘要資訊取自各篇刊載內容。