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題 名 | ADSL等化器之設計與實現=An Equalizer Design and Implementation for ADSL Transceiver |
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作 者 | 陳信勇; | 書刊名 | 電信研究 |
卷 期 | 33:1 2003.02[民92.02] |
頁 次 | 頁157-174 |
分類號 | 448.6 |
關鍵詞 | 通道等化器; Asymmetric digital subscriber line; ADSL; Discrete multitone; DMT; Time domain equalizer; TEQ; Cyclic prefix; CP; Intersymbol interference; ISI; Frequency domain equalizer; FEQ; Frame head detection; FHD; |
語 文 | 中文(Chinese) |
中文摘要 | 通道等化器主要功能為補償傳輸信號經過通道的振幅衰減及相位失真。等化器設計的好壞深遠地影響傳輸品質。ADSL的傳輸通道具有延遲時間長、衰減大且多樣化等特性。等化器無法用單一解來補償不同傳輸通道所造成的失真,其演算法的複雜度和運算量相對增大。因此,等化器在ADSL傳收機設計實現上具有相當重要的地位。本文是選擇適合在數位信號處理器的等化器係數求取演算法,進行探討設計並改進其缺點。在針對時域等化器係數求取,我們使用通道設計特性求得信號延遲點,用來決定時域訊號在LMS適應性演算法所需的等化器延遲時間(∆),以節省反覆計算在不同等化器延遲時間的最佳解所需時間。頻域等化器的設計重點在於如何決定接收信號的每一獨立symbol區間(frame同步),以正確解調接收信號。再利用發送訓練信號求得頻域等化器係數。我們在TI C6201 DSP上實現並驗證其可行性。 |
英文摘要 | Channel equalization plays a crucial role in ADSL transceiver design. It impacts significantly on the transmission performance of the system. Equalizer is required to compensate the channel distortion caused on the transmitted signal. The equalization of ADSL is a MCM (MultiCarrier Modulation) equalization problem, which is usually implemented via a Time Domain Equalizer (TEQ) and a Frequency Domain Equalizer (FEQ). ADSL channels exhibit different delay responses because of the actual physical loops being deployed, therefore no single fixed equalizer solution will fit all channels and online training is required. In this paper, we will discuss a TEQ algorithm suitable for DSP implementation and propose a feasible solution for determining the delay of the channel that is a prerequisite during the training process. In addition the structure of the adaptive algorithm for FEQ is described in details. Both the TEQ and FEQ algorithms are evaluated and implemented on a TI C6201 DSP. |
本系統中英文摘要資訊取自各篇刊載內容。