頁籤選單縮合
題 名 | Design of a Continuous-Time 3□-Order Delta-Sigma Modulator with Incremental Data Weighted Averaging |
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作 者 | Tsai, Ming-Chung; Lin, Tsung-Hsien; | 書刊名 | International Journal of Electrical Engineering |
卷 期 | 14:3 2007.06[民96.06] |
頁 次 | 頁157-165 |
分類號 | 471.661 |
關鍵詞 | ADC; Comparator; DAC; Data-weighted averaging; Dalta-sigma modulator; Dynamic element matching; Quantizer; |
語 文 | 英文(English) |
英文摘要 | A delta-sigma modulator designed for narrowband wireless communication applications is presented in this paper. A continuous-time third-order feedback topology with a 4-bit quantizer is employed in considering the design tradeoffs among power consumption, signal-to-noise ratio (SNR), and other requirements. To relax the stringent linearity requirement of the feedback current-steering digital-to-analog converter (DAC), the in-cremental data-weighted averaging technique is adopted. The proposed modulator achieves a 77-dB peak SNR in a 100-kHz bandwidth with a 24-MHz sampling rate. This chip is fabricated in the TSMC 0.18-µm CMOS process. It consumes 4.5 mW under a 1.8-V supply voltage. |
本系統中英文摘要資訊取自各篇刊載內容。