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題 名 | Automatic Simulation and Verification of Pipelined Microcontrollers |
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作 者 | 黃英哲; 王儷蓉; | 書刊名 | Journal of Information Science and Engineering |
卷 期 | 15:2 1999.03[民88.03] |
頁 次 | 頁307-320 |
分類號 | 448.57 |
關鍵詞 | Functional verification; Simulation; High level synthesis; Microcontrollers; Microprocessors; |
語 文 | 英文(English) |
英文摘要 | This paper presents a methodology for automatic simulation and verification of pipelined microcontrollers. Using this methodology, we can generate the simulation for the instruction set architecture (ISA), abstract finite state machine (FSM) and pipelined register transfer level design and compare the simulation results across different levels quickly. We have implemented our method in the simulation and verification of a synthesized microcontroller HT_4 using our behavioral synthesis tool. |
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