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題名 | Fast VCO Frequency Calibration Techniques for PLL Applications=利用UHVCVD來製造之矽鍺碳層其成長與特性 |
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作者 | 林宗賢; 賴宥任; 許瑞麟; Lin, Tsung-hsien; Lai, Yu-jen; Syu, Ruei-lin; |
期刊 | 國立臺灣大學工程學刊 |
出版日期 | 20050200 |
卷期 | 93 民94.02 |
頁次 | 頁31-38 |
分類號 | 448.552 |
語文 | eng |
關鍵詞 | 鎖相迴路; 選頻; 低相位雜訊; PLL; Synthesizer; Calibration; Phase noise; |
中文摘要 | 本篇論文介紹10-GHz CMOS製程除整數鎖相迴路,並且提出兩種具有快速選頻機制的VCO調變方法。所提出的方法,可以自動且快速地從許多條tuning curve中選出最佳化的一條,所需的時間相較於現在選頻的方法快出很多。不同於現有的計數訊號週期或是於迴路鎖定後比較VCO控制電壓等方法,此晶片提出的是比較訊號的週期。除了快速選頻方法外,為了改善PLL輸出phase noise,不同於以往VCO以電流源偏壓的方式,本顆晶片VCO偏壓是採用PTTA (programmable triode transistor array) 方式以求產生較少的雜訊。此鎖相迴路晶片於低電流模式功率消耗為44毫瓦特,選頻時間小於4 微秒。所採用的製程為0.18-μm CMOS製程。 |
英文摘要 | This paper reports two fast VCO frequency calibration techniques and their applications on a 10-GHz CMOS integer-N phase-locked loop. The proposed methods automatically search for the optimum VCO tuning curve out of a group of curves using much less time than other existing approaches. The agility is due to the novel searching technique which is based on the comparison of signal periods, rather than counting signal cycles or reading the VCO control voltage after the PLL settled. This work further proposes employing a programmable triode transistor array to establish VCO biasing current instead of the tail current source, in order to lower the noise contribution from the tail current transistors. The PLL incorporating the proposed techniques is implemented in a 0.18-μm CMOS process. The PLL consumes 44 mW in low-current mode. The calibration time is less than 4 μsec. |
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