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題名 | 以場效可程式化邏輯陣列為導向的二維封包分類演算法之研究=On FPGA Based Two-dimensional Packet Classification Algorithms |
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作者姓名(中文) | 吳其政; 吳家榮; 邱煌森; | 書刊名 | 龍華科技大學學報 |
卷期 | 20 民94.12 |
頁次 | 頁61-66 |
分類號 | 312.49 |
關鍵詞 | 路由器; 封包分類; 二元決策圖; 場效可程式化邏輯陣列; Router; Packet classification; Binary decision diagrams; BDDs; FPGA; |
語文 | 中文(Chinese) |
中文摘要 | 由於網際網路的快速發展,網際網路訊務的增加需要高速的連線速度和路由器,目前已有10Gbps OC-192光纖線路,因此網際網路訊務的主要瓶頸已由網路線路轉移至路由器。另一方面,網際網路服務提供者會希望路由器能提供差異性服務的功能。但是傳統的路由器主要是查詢IP封包的目的位址來決定封包的下一站位址,因此傳統的路由器對於所有相同目的的位址之封包的處理並無分別,所以它無法提供差異性服務的功能。具有封包分類的路由器能夠根據封包的目的位址、來源位址、目的埠、來源埠和通訊協定類別等欄位來分類封包。這種多欄位封包分類能提供各種不同的型式的差異性服務;例如:阻擋有危害安全的封包進出某網路(如防火牆),服務品質路由,以及資源保留服務等。然而,在封包的各欄位中,處理目的位址和來源位址視為主要的瓶頸所在,本論文使用二元決策圖方法設計出二維(來源位址,目的位址)的封包分類器演算法,二元決策圖具有節點共享的優點,刪除重複的節點,有效率地降低組合電路的成本,而且可運用管線化的技術來提升整體封包分類的處理速度,是一個適合場效可程式化邏輯陣列實現的演算法,我們成功的將它以場效可程式化邏輯陣列硬體實現。 |
英文摘要 | The Internet traffic is rapidly growing not only because of the increase of users but also because of the multimedia applications. With the increased traffic, fast link speed and routers are required. Currently, gigabit links are available (such as OC-192). The chief bottleneck of the traffic has moved from the links to the routers. Meanwhile, the Internet Service Providers (IPSs) would like to provide the differentiated services. The traditional routers lookup routing table for next-hop address based on packet's destination IP address. That is, the routers treat all the packets with the same destination address identically. Thus, the traditional routers cannot provide the functions of differentiated service. A packet classification router based on multi-field from the packet header fields, such as destination and source IP addresses, destination and source ports, and protocol type. The multi-field packet classification can provide various types of differentiated service include of Virtual Private networks (VPNs), packet filtering in firewalls, QoS routing, and RSVP. Consequently, multi-field packet classification has become an essential component of next generation routers and firewalls. However, the multi-field packet classification has proved to be far more difficult and take more CPU time. Recently, several methods have been proposed for packet classification. Although some of these methods provide fast packet classify performance, require O(n[fee2]) memory. Warkkhede et al. show a two-field packet classification, a binary tuple-space search methods, requires O(nlog²w) memory. In this paper, we propose a binary decision diagrams (BDDs) based combinational circuit for an efficient implementation of fast-two-dimensional packet classification scheme in reconfigurable hardware, FPGA. |
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