頁籤選單縮合
題名 | Memory-Efficient and Fast Architectures for Forward and Inverse DCT with Multiplierless Operation= |
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作者 | Sung, Tze-yun; Shieh, Yaw-shih; Hsin, Hsi-chin; |
期刊 | Chung Hua Journal of Science and Engineering |
出版日期 | 20061200 |
卷期 | 4:4 民95.12 |
頁次 | 頁23-28 |
分類號 | 312.1 |
語文 | eng |
關鍵詞 | DCT; IDCT; Parallel-pipelined; Memory-efficiency; High-performances; |