頁籤選單縮合
題名 | A Novel CAM/RAM Based Buffer Manager for New Generation IP Routers= |
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作者 | Dou, Chie; Jiang, Shing-jeh; |
期刊 | International Journal of Electrical Engineering |
出版日期 | 20050800 |
卷期 | 12:3 民94.08 |
頁次 | 頁233-244 |
分類號 | 312.13 |
語文 | eng |
關鍵詞 | Content addressable memory; Buffer management; IP router; Data buffer; |
英文摘要 | Content Addressable Memory (CAM) technology delivers highly scaleable and high performance solutions for evolving network applications like packet classification and flow identification. This paper proposes an innovative CAM/RAM based buffer manager for managing packet buffering and releasing procedures in the data buffer for next generation IP routers. Presently, most of the IP routers use fixed-length memory blocks for buffering packets. If a packet is larger than the size of a memory block, the buffer manager is responsible for chaining together the memory blocks allocated to the packet. This paper uses an integrated CAM/RAM architecture to implement the buffer management operations of the buffer manager by hardware. The functions of conventional soft-maintained free buffer list and its associated pop and return operations can be replaced by hardware CAM/RAM operations. In addition, the proposed buffer manager adopts a novel buffer allocation scheme that can allocate incoming packets with different-size memory blocks, so the wasted buffer area and the number of pointers for chaining together the packet in the data buffer are minimized. The proposed CAM/RAM architecture also supports the multicast management in an elaborate manner. The flexibility of the CAM allows the data buffer to be configured according to the packet size distribution observed from the underlying network thus increasing the efficiency of the memory utilization. This paper extends the applications of CAM/RAM architecture to future high-speed packet switching. |
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