頁籤選單縮合
題 名 | A Low-Jitter Phase-Interpolation Direct Digital Synthesizer using Single Capacitor Integration |
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作 者 | Chen, Hsin-chuan; Chiang, Jen-shiun; | 書刊名 | International Journal of Electrical Engineering |
卷 期 | 12:3 民94.08 |
頁 次 | 頁225-232 |
分類號 | 448.532 |
關鍵詞 | Direct digital frequency synthesizer; DDS; Phase accumulator; Phase interpolation; Single capacitor integration; Phase jitter; |
語 文 | 英文(English) |
英文摘要 | There exists a phase jitter problem in using the conventional DDS as a pulse or clock generator. In this paper, a new phase-interpolation DDS scheme is proposed, which uses the output of the phase accumulator to provide an initial voltage on an integration capacitor in the first phase, and then performs integration operation on the same integration capacitor in the second phase. By using single capacitor integration, the output time intervals are almost independent of component variations under acceptable error, and the instability of the delay generator can be avoided. Therefore, the proposed DDS without ROM tables can achieve a low-jitter clock output. |
本系統中英文摘要資訊取自各篇刊載內容。