頁籤選單縮合
題 名 | An Efficient VLSI Architecture for Rivest-Shamir-Adleman Public-key Cryptosystem |
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作 者 | Chiang,Jen-shiun; Chien,Cheng-chih; Chen,Jian-kao; Chou,Hsin-guo; | 書刊名 | 淡江理工學刊 |
卷 期 | 7:4 2004.12[民93.12] |
頁 次 | 頁241-250 |
分類號 | 312.76 |
關鍵詞 | Data security; H-algorithm; L-algorithm; Modular exponentiation; Modular multiplication; Montgomery's algorithm; Public-key cryptosystem; RSA; VLSI; |
語 文 | 英文(English) |
英文摘要 | In this paper, a new efficient VLSI architecture to compute modular exponentiation and modular multiplication for Rivest-Shamir-Adleman (RSA) public-key cryptosystem is proposed. We modify the conventional H-algorithm to find the modular exponentiation. By this modified H-algorithm, the modular multiplication steps for n-bit numbers are reduced by 5n/18 times. For the modular multiplication a modified L-algorithm (LSB first) is used. In the architecture of the modified modular multiplication the iteration times are only half of Montgomery's algorithm and the H-algorithm. The proposed architecture for the RSA public-key crypto-system has a data rate of 146 kb/s for 512-b words with a 200-MHz clock rate. |
本系統中英文摘要資訊取自各篇刊載內容。