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題 名 | Design of a New Divider/Multiplier Fused Unit for Floating-Point Arithmetic |
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作 者 | Chen,Chichyang; Yen,Hsin-lin; Sheu,Ming-hwa; | 書刊名 | International Journal of Electrical Engineering |
卷 期 | 11:3 2004.08[民93.08] |
頁 次 | 頁239-246 |
分類號 | 448.57 |
關鍵詞 | Floating-point multiplication and division; Signed-digit adder; Signed-digit multiplier; Division-by-reciprocal algorithm; |
語 文 | 英文(English) |
英文摘要 | Design of a new divider/multiplier fused unit that can be used in a high-performance floating-point microprocessor is proposed. Signed-digit (SD) division-by-reciprocal algorithm and termination algorithm are introduced to design the divider. On the other hand, a linear SD multiplier and a binary-tree SD multiplier are proposed to implement the multiplier in the fused unit. The shift-and-add operation for the SD division-by-reciprocal algorithm can be implemented on a fast SD adder and can also be utilized to implement the linear SD multiplier. Furthermore, the binary-tree SD multiplier for the termination algorithm can be shared to implement the multiplier in the fused unit. Based on the proposed multiplier and divider algorithms, a 24-bit multiplier/divider fused unit for IEEE single-precision floating-point multiplication/division is designed. Synthesis results of this 24-bit fused unit show that the amount of the area saving for a 24-bit SD multiplier and a 24-bit SD division-by-reciprocal divider can be adjusted easily by changing the number of the shared normalization stages in the divider circuit. We conclude that the proposed approach for divider/multiplier fused unit can make flexible trade-off between the amount of hardware sharing and the speed of the multiplier in the design of arithmetic processors that require both high-speed floating-point division and multiplication. |
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