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題 名 | A Unified Approach to Object-Oriented VHDL |
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作 者 | Radetzki,Martin; Wolfram,Putzke-roming; Nebel,Wolfgang; | 書刊名 | Journal of Information Science and Engineering |
卷 期 | 14:3 1998.09[民87.09] |
頁 次 | 頁523-545 |
分類號 | 448.57 |
關鍵詞 | Hardware; Design; Modeling; System level; Reuse; Object-oriented; VHDL; |
語 文 | 英文(English) |
英文摘要 | Abstraction and reuse are keys to dealing with the increasing complexity of electronic systems. We apply object-oriented modeling to achieve more reuse and higher abstraction in hardware design. This requires an object-oriented hardware description language, preferably an extension of VHDL. Several variants of such OO-VHDL are currently being debated. We present our unified approach. Objective VHDL. which adds object-oriented features to the VHDL design entity as well as to the types system to provide maximum modeling power. |
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