頁籤選單縮合
題名 | Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits= |
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作者 | 呂昭宏; 陳宏明; 劉建男; Lu, Chao-hung; Chen, Hung-ming; Liu, Jimmy Chien-nan; |
期刊 | Journal of Information Science and Engineering |
出版日期 | 20110100 |
卷期 | 27:1 2011.01[民100.01] |
頁次 | 頁287-302 |
分類號 | 448.532 |
語文 | eng |
關鍵詞 | Stacking IC; Partition; Floorplanning; TSV; 3D-via; |