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題名 | 可電壓控制之電源模式感知時脈樹=Voltage-controllable Power-mode-aware Clock Tree |
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作者 | 聶佑庭; 黃世旭; 張世杰; 周仲韓; 凃雯斌; Nieh, Yow-tyng; Huang, Shih-hsu; Chang, Shih-chieh; Chou, Chung-han; Tu, Wen-pin; |
期刊 | 電腦與通訊 |
出版日期 | 20131200 |
卷期 | 154 2013.12[民102.12] |
頁次 | 頁11-16 |
分類號 | 448.57 |
語文 | chi |
關鍵詞 | 時脈樹; 時脈差異; 電源模式; Clock tree; Clock skew; Power mode; |
中文摘要 | 當晶片電壓降到超低電壓範圍,處於不同電源模式間的時序收斂問題,成為了一項嚴峻的挑戰。由於晶片電壓變動的範圍極大,巨大的時序差異常常發生在不同的電源模式之間。為了要降低時脈差異,我們發現,傳統的電源感知時脈樹會造成過多的功率消耗。本篇論文所提出的可電壓控制之電源感知時脈樹結構,可利用不同電源模式資訊,選擇適當的操作電壓與時脈延遲通道,在面積與功率消耗上都可獲致明顯的改善。 |
英文摘要 | As the supply voltage is down to the ultra-low voltage (ULV) level, timing closure becomes a serious challenge in the use of multiple power modes. Due to a wide voltage range, a very huge clock skew may occur among different power modes. To reduce this huge clock skew, the conventional power -mode-aware clock tree often suffers from a huge overhead on power consumption. In this paper, we propose a power-mode-aware clock tree structure to select the supply voltage and the buffer chain channel at the same time; as a result, both the area and the power consumption can be improved. |
本系統之摘要資訊系依該期刊論文摘要之資訊為主。