頁籤選單縮合
題 名 | Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs |
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作 者 | Rau, Jiann-chyi; Wu, Po-han; Huang, Wnag-tiao; Chien, Chih-lung; Chen, Chien-shiun; | 書刊名 | 淡江理工學刊 |
卷 期 | 13:3 2010.09[民99.09] |
頁 次 | 頁305-314 |
分類號 | 440.12 |
關鍵詞 | Test access mechanism; TAM; Test application time; Core-based SOCs; |
語 文 | 英文(English) |
英文摘要 | Abstract In this paper, we propose an algorithm based on a framework of reconfigurable multiple scan chains for system-on-chip to minimize test application time. The control signal combination causes the computing time increasing exponentially, and the algorithm we proposed introduces a heuristic control signal selecting method to solve this serious problem. We also minimize the test application time by using the balancing method to assign registers into multiple scan chains. The results show that it could significantly reduces both the test application time and the computation time. |
本系統中英文摘要資訊取自各篇刊載內容。