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題名 | The FPGA Chip Design of the Forward and Backward Discrete Cosine Transform=數位餘弦轉換與反轉換之FPGA晶片設計 |
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作者 | 陳文淵; 劉正忠; 羅瑞麟; | 書刊名 | 勤益學報 |
卷期 | 23:2 民94.12 |
頁次 | 頁21-37 |
分類號 | 448.57 |
關鍵詞 | 數位餘弦轉換; 數位餘弦反轉換; 晶片設計; Discrete cosine transform; FDCT; Inverse discrete cosine transform; IDCT; Very high speed description language; VHDL; Field programmable gate array; FPGA; |
語文 | 英文(English) |
中文摘要 | 數位餘弦轉換(discrete cosine transform, DCT)與數位餘弦反轉換(inverse discrete cosine transform, IDCT),因轉換後的連續特性較數位傅立葉轉換(discrete fourier transform, DFT)的特性佳,因此大量的被使用在數位信號處理(digital signal processing, DSP)及影像處理(image processing)上,尤其是在影像壓縮方面。數位餘弦轉換與反轉換的轉換過程,需極大的運算量,以一個8×8的區塊轉換來說,數位餘弦轉換需要64×64×3個餘弦乘法及64×64×2個加法運算。若以一張512×512的影像進行一次的數位餘弦轉換,需要的運算量為4096×((64×64×3×cos(θ))+(64×64×2×(+)))。如何解決這耗時的缺點?當然只有將數位餘弦轉換與反轉換設計成IC,以硬體方式來完成值這耗時的工作。 在本文中我們將DCT與IDCT的數學式,以硬體描述語言(very high speed description language, VHDL)來設計,將其硬體化,製作成一顆FPGA的IC。在電路結構上將其分成五大部分即:(1)資料I/O,安排較佳的資料提取順序,降低處理資料的時間。(2)數值運算器,將提取的資料做三次乘法運算,及初步的有效位元調整。(3)累加調整器,調整資料的累加誤差值。(4)精度調整器,消除根號運算所產生的細微誤差值。(5)位址發送器,負責計算及擷取資料的位址,決定累加調整器和精度調整器的調整值,兼處理整個程式的計數工作。電路完成後,經模擬測試後結果顯示,DCT與IDCT的運算均能得到正確的結果。再以影像資料經DCT轉換及IDCT轉換測試也都得到正確的結果,這證明了本晶片電路的設計是正確成功的。 |
英文摘要 | The continuity characteristic of a signal that is transformed by the forward discrete cosine transform (FPDC) and then is transformed by the inverse discrete cosine transform (IDCT) is better than that is transformed by the discrete Fourier transformation (DFT). It is the reason why FDCT and IDCT are frequently used in digital signal processing (DSP) or in image processing, especially in image compression. The discrete cosine transform and inverse discrete cosine transform need a host of mathematical operations; for a discrete cosine transform of a 8×8 image block, it needs 64×64×3 multiplication operations of cosine terms and 64×64×2 addition operations. Similarly the number of multiplication operations of cosine terms is 4096×64×64×3, and the number of addition operations is 4096×64×64×2 for a discrete cosine transform of a 512×512 image. How do we solve the taking huge time problems in FDCT and in IDCT? The best technique is to synthesize an IC possessing FDCT and IDCT simultaneously, then to handle the taking time works with a hardware IC. In this paper, we design and synthesize a FPGA chip of FDCT and IDCT with the very high speed description language (VHDL) to describe its mathematical formulas. In circuit design, there are five parts in our FDCT & IDCT IC chip; (A) Data I/O: it arranges the sequence of data collecting to reduce the time of data procession. (B) Numerical Operator: it does arithmetical multiplication operations three times for these collection data in (A) and adjusts the efficient bits of these collection data. (C) Accumulation-Adjuster: it adjusts the accumulated error of data. (D) Precise Adjuster: it eliminates the slight error produced in the square root operation. (E) address-Teller: it calculates and extracts the addresses of collecting data, finds the adjustment value of the Accumulation-Adjustor, and manipulates the counting of whole program. To explore the utility and demonstrate the efficiency of the proposed scheme, simulations under various conditions are conducted. The results of simulation and experiment show that our chip works well in DCT and IDCT operation. |
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