頁籤選單縮合
題名 | Entity Overloading for Mixed-Signal Abstraction in VHDL= |
---|---|
作者 | Shi,Richard C. -J.; |
期刊 | Journal of Information Science and Engineering |
出版日期 | 19980900 |
卷期 | 14:3 1998.09[民87.09] |
頁次 | 頁633-643 |
分類號 | 448.57 |
語文 | eng |
關鍵詞 | Mixed-Signal Abstraction; VHDL; |
英文摘要 | In this paper we propose to extend VHDL with entity overloading. With minimal change in the existing VHDL, entity overloading provides strong support for mixed-signal, mixed-level, and mixed-domain abstractions. It is particularly promising for resolving some issues related to analog extension of VHDL. Furthermore, we show that entity overloading can be combined with certain modeling rules to obtain a polymorphic netlist. |
本系統之摘要資訊系依該期刊論文摘要之資訊為主。