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題名 | Control/Data-Flow Analysis for VHDL Semantic Extraction= |
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作者 | Hsieh,Yee-wing; Levitan,Steven P.; |
期刊 | Journal of Information Science and Engineering |
出版日期 | 19980900 |
卷期 | 14:3 1998.09[民87.09] |
頁次 | 頁547-565 |
分類號 | 448.57 |
語文 | eng |
關鍵詞 | VHDL semantics extraction; Memory semantics extraction; Control/data-flow analysis; Model partitioning; Model abstraction; |
英文摘要 | Model abstraction reduces the number of states necessary to perform formal verification while maintaining the functionality of the original model with respect to the specifications to be verified. However, in order to perform model abstraction, we must extract the semantics of the model itself. In this paper. We describe a method for extracting VHDL semantics for model abstraction to improve the performance of formal verification tools such as COSPAN. |
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